The present invention relates generally to integrated circuits, and, more particularly, to a delay lock loop circuit.
Clock signals are used in virtually every integrated circuit (IC) to control the operational timing of the IC and/or the transfer of data within and between ICs. For example, all individual circuits or devices, such as, for example, flip-flops and/or latches, in a given IC may change state on a single rising or falling edge of a common clock signal. Relatively large ICs, such as, for example, memory chips and programmable logic arrays, include thousands or even millions of such individual circuits or devices. The clock signal is typically applied to a clock input pin of the IC for distribution to each of those numerous devices throughout the IC. Thus, the clock signal is transmitted or propagated from the clock input pin to devices on the IC that are both relatively near to and relatively distant from the clock input pin. By the time the clock signal reaches the devices that are disposed on portions of the IC that are relatively remote from the input pin, the clock signal is likely to have suffered significant propagation delay.
The clock signal received at the IC clock input is hereinafter referred to as the input or reference clock signal REF_CLK, whereas the clock signal received by the last-served device on the IC is hereinafter referred to as the propagated clock signal P_CLK. The propagation delay between the REF_CLK and P_CLK signals, designated hereinafter as tP, may cause difficulties in interfacing between ICs and/or slow down the overall operating speed of a system. For example, data may be provided or input to an IC in a time-aligned manner relative to the reference clock signal, whereas data output from the IC is likely to be provided in a time-aligned manner with the propagated clock signal.
The propagation delay tP for a particular IC is dependent at least in part upon the configuration of that particular IC. Thus, for a given IC tP operating at standard or rated operating conditions, temperatures and voltages, tP will generally not vary substantially. However, tP will vary due to external factors, such as, for example, changes in ambient temperature and/or applied voltage. It is beneficial to compensate for the effect of such external factors on the propagation delay tP of the reference clock signal by time-aligning the propagated clock signal P_CLK of an IC with the reference clock signal REF_CLK. Delay lock loop circuits are one way in which such time alignment of signals is performed.
Delay lock loop (DLL) circuits receive the reference clock signal REF_CLK and produce an output clock signal CLK_OUT that is advanced or delayed relative to the reference clock signal REF_CLK. For convenience, all signals produced by a DLL will hereinafter be referred to as being delayed relative to the REF_CLK signal regardless of whether the particular signal is actually advanced or delayed relative to the reference clock signal. A DLL delays the output clock signal CLK_OUT by an amount of time that is approximately equal to the propagation delay tP of the IC, i.e., the amount of time required for the reference clock signal REF_CLK to propagate through the IC under standard or normal operating conditions. Further, a DLL adjusts the CLK_OUT signal to compensate for changes in tP due to the aforementioned external factors. Devices formed on portions of the IC that are proximate the clock input pin are typically supplied with the REF_CLK signal, whereas devices formed on portions of the IC relatively distant from the input clock signal are typically supplied with the CLK_OUT signal via on off chip driver. Thus, all devices on the IC receive clock signals that are aligned in time.
The DLL adjusts the amount of time by which the CLK_OUT signal is delayed relative to the REF_CLK signal by comparing the REF_CLK signal to a feedback clock signal FB_CLK that models the propagation delay of the IC. The CLK_OUT signal is essentially a delayed version of the REF_CLK signal. The delay of the CLK_OUT signal is adjusted by a forward delay circuit having a forward delay line. The forward delay line includes a plurality of individual delay units, such as, for example, a predetermined number of buffers or invertors connected together in series. The length of the forward delay line is adjusted based upon a comparison of the REF_CLK signal to the feedback clock signal FB_CLK, to thereby adjust the delay of the CLK_OUT signal relative to the REF_CLK signal.
Generally, a DLL must provide a minimum delay time approximately equal to the longest anticipated cycle time (i.e., the lowest operating frequency) of the REF_CLK signal to ensure alignment of the REF_CLK signal with the FB_CLK signal under worst-case operating conditions. In relatively high-frequency applications, such as, for example, in dynamic random access memory (DRAM) chips or other ICs that require clock skew adjustment, the entire length of the delay line is rarely required. Thus, a substantial portion of the delay line may not be necessary under normal operation of the IC.
Therefore, what is needed in the art is a DLL that selectively deactivates the portion of the delay line that is not necessary.
Furthermore, what is needed in the art is a DLL that reduces power consumption by clocking only those sections of the delay line that are necessary to time-align the clock signals.
Moreover, what is needed in the art is a DLL that reduces the load on the system or reference clock signal by deactivating unused sections of the delay line.
The present invention provides a delay lock loop circuit that selectively deactivates blocks of delay units that are not necessary for aligning a reference clock signal with an internal feedback clock signal.
The invention comprises, in one form thereof, a forward delay circuit that receives the reference clock signal. The forward delay circuit includes a forward delay line having a plurality of electrically interconnected delay blocks. Each of the delay blocks includes a predetermined number of electrically interconnected delay units. Disabling means disable the one or more delay blocks when the delay blocks are not needed in order to time align the reference clock signal with the internal feedback clock signal.
An advantage of the present invention is that the portion of the delay line that is not necessary is deactivated.
Another advantage of the present invention is that power consumption is reduced by clocking only those sections of the delay line that are necessary.
Yet another advantage of the present invention is that the load on the reference clock signal is reduced by deactivating unused sections of the delay line.